Dr. Prasad M
Assistant Professor
About
I am Dr. Prasad M, an academician and researcher specializing in Electronics Engineering, VLSI, semiconductor device modelling, and nanotechnology.
I currently serve as an Assistant Professor in School of Engineering (ECE) at RV University, Mysuru.
I completed my Ph.D. in “Modelling and Analysis of Multi-Gate FinFET” from Visvesvaraya Technological University, under the guidance of Dr. U. B. Mahadevaswamy. My academic qualifications also include an M.Tech. in VLSI Design and Embedded Systems and a B.E. in Electronics and Communication Engineering.
My research focuses on advanced semiconductor devices and emerging Nanoscale architectures, particularly FinFETs, Gate-All-Around (GAA) FETs, junctionless FETs, Nanosheets, Nanowires, and semiconductor device modelling. I have published research articles in journals including IEEE Access, IEEE Open Journal of Nanotechnology, IETE Journal of Research, Wireless Personal Communications, and AEU – International Journal of Electronics and Communications. My work covers device performance enhancement, gate-stack engineering, core-shell structures, doping engineering, gate-dielectric engineering, low-power operation, and analog/RF applications.
Alongside research, I have several years of teaching experience at undergraduate and postgraduate levels. I have taught subjects including CMOS VLSI, Verilog, Switching Theory and Logic Design, Microprocessors, and Micro controllers. I am also interested in guiding students in research and project development and contributing to outcome-based education.
My professional interests extend to research proposal development, academic collaboration, emerging semiconductor technologies, and the development of next-generation electronic devices.
This work investigates gate-stack engineering in junctionless Multi-Bridge-Channel FET architectures targeted toward sub-3 nm semiconductor technology. The study focuses on improving device characteristics through appropriate gate-stack design and contributes to the development of advanced nanoscale transistor architectures for future integrated circuits.
This research investigates a novel core-shell junctionless nanosheet FET architecture for CMOS logic applications. The study analyzes device characteristics and explores architectural approaches for improving the performance of nanoscale semiconductor devices. The work contributes to the development of advanced transistor structures suitable for future low-dimensional and high-performance CMOS technologies.
This work examines spacer engineering in multi-channel FinFET structures with a focus on improving device performance for advanced wireless applications. The research explores device-level engineering approaches that can contribute to enhanced electrical characteristics and the development of high-performance nanoscale semiconductor devices.
This research investigates the performance enhancement of vertically stacked quad-gate nanosheet structures through rectangular core-shell architecture, doping engineering, and gate-dielectric engineering. The study focuses on device optimization for advanced nanoscale semiconductor applications.
This study evaluates the performance of vertically stacked quad-gate oxide junctionless nanosheet structures. It contributes to the understanding and optimization of advanced nanosheet transistor architectures for next-generation nanoelectronic applications.
This research analyzes the performance of a tri-gate junctionless FET using trioxide and rectangular core-shell architecture. The work explores structural and material engineering techniques for improving the performance of advanced nanoscale transistor devices.
Research specialization in semiconductor device modelling, VLSI, and nanotechnology.
Ph.D. research focused on modelling and analysis of Multi-Gate FinFETs.
Research on FinFET, Gate-All-Around (GAA) FET, junctionless FET, nanosheet, and nanowire architectures.
Investigation of advanced transistor structures for sub-3 nm and nanoscale semiconductor technologies.
Device-performance enhancement through gate-stack, spacer, doping, core-shell, and gate-dielectric engineering.
Research into low-power semiconductor devices and leakage-current reduction.
Analysis of nanoscale devices for CMOS logic, analog, RF, fast-switching, and advanced wireless applications.
Experience with Visual TCAD 2D/3D for semiconductor device modelling and simulation.
Published research in international journals including IEEE Access, IEEE Open Journal of Nanotechnology, IETE Journal of Research, Wireless Personal Communications, and AEU – International Journal of Electronics and Communications.
Presented research at international conferences covering semiconductor devices, wireless communication, and related electronics technologies.
Research interests include developing and optimizing next-generation nanoelectronic devices for improved performance and energy efficiency.
Research Interests
Semiconductor Device Modelling | FinFET | Gate-All-Around (GAA) FET | Junctionless FET | Nanosheet FET | Nanowire FET | Nanotechnology | VLSI | Nanoelectronics | Low-Power Devices | Advanced CMOS Technology
Ph.D. in Semiconductor Device Modelling
Awarded Ph.D. for research on “Modelling and Analysis of Multi-Gate FinFET” from Visvesvaraya Technological University in 2022.
International Journal Publications
Published research in reputed journals including IEEE Access, IEEE Open Journal of Nanotechnology, IETE Journal of Research, and Wireless Personal Communications.
Published Patents
Two patents published on IoT-based Smart Helmet and Secure Spectrum and Beamforming for Internet of Connected Vehicles.
Academic Teaching Experience
Experienced in teaching undergraduate and postgraduate students across VLSI, digital electronics, microprocessors, microcontrollers, and related subjects.
Research Proposal Development
Prepared project proposals for funding agencies including the Department of Science and Technology (DST) and Science and Engineering Research Board (SERB).
IEEE Conference Session Chair
Served as Session Chair at the IEEE International Conference on Communication, Computer, and Information Technology (IC3IT-2025).
Research Reviewer
Served as a reviewer for international conferences including IACIS-2025 and NMITCON-2025.
AICTE-ATAL Faculty Development Program
Successfully completed the AICTE-ATAL Faculty Development Program on Semiconductor Innovation & Technology for Next-Gen Electronics in 2025.
e-Yantra Laboratory Coordinator
Contributed as coordinator for e-Yantra laboratory setup and participated in the e-Yantra Robotics Teacher Competition.
Semiconductor Device Modelling Expertise
Developed research expertise using Visual TCAD 2D/3D and related semiconductor and IC-design tools for advanced device modelling and simulation.
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